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ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
13 years 7 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
ICCAD
1997
IEEE
134views Hardware» more  ICCAD 1997»
14 years 1 months ago
Post-route optimization for improved yield using a rubber-band wiring model
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
Jeffrey Z. Su, Wayne Wei-Ming Dai
GD
2007
Springer
14 years 3 months ago
Constrained Stress Majorization Using Diagonally Scaled Gradient Projection
Abstract. Constrained stress majorization is a promising new technique for integrating application specific layout constraints into forcedirected graph layout. We significantly i...
Tim Dwyer, Kim Marriott
AICCSA
2005
IEEE
103views Hardware» more  AICCSA 2005»
14 years 3 months ago
Consistent graph layout for weighted graphs
In this paper we present three algorithms that build graph layouts for undirected, weighted graphs. Our goal is to generate layouts that are consistent with the weights in the gra...
Dana Vrajitoru, Jason DeBoni
IEEEPACT
2006
IEEE
14 years 3 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...