This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
Abstract. Constrained stress majorization is a promising new technique for integrating application specific layout constraints into forcedirected graph layout. We significantly i...
In this paper we present three algorithms that build graph layouts for undirected, weighted graphs. Our goal is to generate layouts that are consistent with the weights in the gra...
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...