2201 search results - page 148 / 441 » Improvement of ASIC Design Processes |
126
Voted
ICCAD
1994
IEEE
15 years 7 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
125
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ISQED
2007
IEEE
15 years 9 months ago
2007
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
137
Voted
DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and ev...
125
Voted
TVLSI
2008
15 years 2 months ago
2008
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result s...
148
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ICIP
2010
IEEE
15 years 1 months ago
2010
IEEE
Copy-move tampering is a common type of image synthesizing, where a part of an image is copied and pasted to another place to add or remove an object. In this paper, an efficient ...