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» Improvement of ASIC Design Processes
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ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 4 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
13 years 6 months ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...
DSD
2003
IEEE
108views Hardware» more  DSD 2003»
14 years 23 days ago
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique
This paper presents a method with an evolutionary approach to some of the tasks of integrated-circuit (IC) design. The work is focused on application-specific integrated circuits ...
Gregor Papa, Jurij Silc
CASES
2004
ACM
14 years 27 days ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
14 years 1 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman