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» Improvement of ASIC Design Processes
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FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 12 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
14 years 7 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
14 years 1 months ago
A high-speed low-energy dynamic PLA using an input-isolation scheme
— Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic ...
Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh
DSD
2003
IEEE
106views Hardware» more  DSD 2003»
14 years 23 days ago
Analytical Bounds on the Threads in IXP1200 Network Processor
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
S. T. G. S. Ramakrishna, H. S. Jamadagni
CDVE
2004
Springer
114views Visualization» more  CDVE 2004»
14 years 26 days ago
Observing Architectural Design: Improving the Development of Collaborative Design Environments
The physical environments in which design collaborations take place provide many affordances, which enable interactions to occur both seamlessly and (in most cases) successfully. P...
Matthew Simpson, Stephen Viller