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» Improvement of ASIC Design Processes
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155
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AIA
2007
15 years 5 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann
104
Voted
BIOSYSTEMS
2007
52views more  BIOSYSTEMS 2007»
15 years 3 months ago
The genotypic complexity of evolved fault-tolerant and noise-robust circuits
Noise and component failure is an increasingly difficult problem in modern electronic design. Bioinspired techniques is one approach that is applied in an effort to solve such is...
Morten Hartmann, Pauline C. Haddow, Per Kristian L...
129
Voted
CODES
2005
IEEE
15 years 9 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
117
Voted
DAC
2003
ACM
16 years 4 months ago
Learning from BDDs in SAT-based bounded model checking
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
126
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VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
16 years 4 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...