2201 search results - page 4 / 441 » Improvement of ASIC Design Processes |
CDES
2006
13 years 8 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ENTCS
2006
13 years 7 months ago
2006
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
DATE
2002
IEEE
14 years 12 days ago
2002
IEEE
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
- This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The prop...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...