2201 search results - page 5 / 441 » Improvement of ASIC Design Processes |
ITCC
2005
IEEE
14 years 1 months ago
2005
IEEE
In many applications a software implementation of ECC (Elliptic Curve Cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
ISCAS
2003
IEEE
14 years 22 days ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...