37 search results - page 4 / 8 » Improving Execution Speed of FPGA using Dynamically Reconfig... |
FCCM
1998
IEEE
13 years 11 months ago
1998
IEEE
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...