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» Improving IEEE 802.11 power saving mechanism
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HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
14 years 1 months ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 8 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
DAC
2008
ACM
14 years 9 months ago
Control theory-based DVS for interactive 3D games
We propose a control theory-based dynamic voltage scaling (DVS) algorithm for interactive 3D game applications running on batterypowered portable devices. Using this scheme, we pe...
Yan Gu, Samarjit Chakraborty