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» Improving IEEE 802.11 power saving mechanism
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MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 3 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
DEXAW
2005
IEEE
263views Database» more  DEXAW 2005»
14 years 2 months ago
Energy Aware Routing Protocol for Heterogeneous Wireless Sensor Networks
In this paper we present Energy Aware Random Asynchronous Wakeup (RAW-E), a novel crosslayer power management and routing protocol for heterogeneous wireless sensor and actor netw...
Vamsi Paruchuri, Arjan Durresi, Leonard Barolli
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
14 years 1 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 3 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 1 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...