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» Improving Java performance using hardware translation
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121
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USENIX
2003
15 years 4 months ago
The Design of the {OpenBSD} Cryptographic Framework
Cryptographic transformations are a fundamental building block in many security applications and protocols. To improve performance, several vendors market hardware accelerator car...
Angelos D. Keromytis, Jason L. Wright, Theo de Raa...
112
Voted
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
15 years 9 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
116
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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
15 years 9 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
133
Voted
CF
2007
ACM
15 years 6 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
SIGMETRICS
2008
ACM
121views Hardware» more  SIGMETRICS 2008»
15 years 2 months ago
Disk scrubbing versus intra-disk redundancy for high-reliability raid storage systems
Two schemes proposed to cope with unrecoverable or latent media errors and enhance the reliability of RAID systems are examined. The first scheme is the established, widely used d...
Ilias Iliadis, Robert Haas, Xiao-Yu Hu, Evangelos ...