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» Improving Java performance using hardware translation
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115
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SOSP
1997
ACM
15 years 4 months ago
Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
Robert Stets, Sandhya Dwarkadas, Nikos Hardavellas...
119
Voted
WWW
2007
ACM
16 years 3 months ago
Globetp: template-based database replication for scalable web applications
Generic database replication algorithms do not scale linearly in throughput as all update, deletion and insertion (UDI) queries must be applied to every database replica. The thro...
Tobias Groothuyse, Swaminathan Sivasubramanian, Gu...
136
Voted
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
15 years 11 months ago
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
124
Voted
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 7 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
15 years 4 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar