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» Improving Java performance using hardware translation
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128
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ISCA
2009
IEEE
143views Hardware» more  ISCA 2009»
15 years 9 months ago
Spatio-temporal memory streaming
Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming r...
Stephen Somogyi, Thomas F. Wenisch, Anastasia Aila...
113
Voted
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
15 years 7 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
111
Voted
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 7 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
152
Voted
SIGMETRICS
2011
ACM
237views Hardware» more  SIGMETRICS 2011»
14 years 5 months ago
Analysis of DCTCP: stability, convergence, and fairness
Cloud computing, social networking and information networks (for search, news feeds, etc) are driving interest in the deployment of large data centers. TCP is the dominant Layer 3...
Mohammad Alizadeh, Adel Javanmard, Balaji Prabhaka...
115
Voted
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 8 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed