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143
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HPCA
2008
IEEE
16 years 2 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
111
Voted
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 9 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
120
Voted
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 9 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 5 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
243
Voted
HPDC
2012
IEEE
13 years 4 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...