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» Improving Java performance using hardware translation
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92
Voted
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
15 years 8 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
15 years 8 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
122
Voted
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
15 years 7 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
SIGGRAPH
2000
ACM
15 years 6 months ago
Illuminating micro geometry based on precomputed visibility
Many researchers have been arguing that geometry, bump maps, and BRDFs present a hierarchy of detail that should be exploited for efficient rendering purposes. In practice howeve...
Wolfgang Heidrich, Katja Daubert, Jan Kautz, Hans-...
SIGMETRICS
1998
ACM
15 years 6 months ago
Scheduling Policies to Support Distributed 3D Multimedia Applications
We consider the problem of scheduling tasks with unpredictable service times on distinct processing nodes so as to meet a real-time deadline, given that all communication among no...
Thu D. Nguyen, John Zahorjan