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» Improving Java performance using hardware translation
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109
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DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 9 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
115
Voted
ACL
2008
15 years 4 months ago
Combining Source and Target Language Information for Name Tagging of Machine Translation Output
A Named Entity Recognizer (NER) generally has worse performance on machine translated text, because of the poor syntax of the MT output and other errors in the translation. As som...
Shasha Liao
94
Voted
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
15 years 11 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
COMPSAC
2008
IEEE
15 years 9 months ago
Ontology Model-Based Static Analysis on Java Programs
1 Typical enterprise and military software systems consist of millions of lines of code with complicated dependence on library abstractions. Manually debugging these codes imposes ...
Lian Yu, Jun Zhou, Yue Yi, Ping Li, Qianxiang Wang
125
Voted
IWSOC
2003
IEEE
132views Hardware» more  IWSOC 2003»
15 years 7 months ago
A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of realtime embedded systems. In particular, the judicious use of specialised d...
Neil W. Bergmann, Peter Waldeck, John A. Williams