315 search results - page 37 / 63 » Improving Performance by Branch Reordering |
INFOVIS
1999
IEEE
14 years 1 months ago
1999
IEEE
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
IPPS
2003
IEEE
14 years 2 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
EDBT
2004
ACM
14 years 9 months ago
2004
ACM
The join operation, which combines tuples from multiple relations, is the most fundamental and, typically, the most expensive operation in database queries. The standard approach t...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
IEEEPACT
2009
IEEE
14 years 3 months ago
2009
IEEE
—CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style re...