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» Improving Performance of Small On-Chip Instruction Caches
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ICDCS
1999
IEEE
13 years 12 months ago
Proxy Cache Coherency and Replacement - Towards a More Complete Picture
This work studies the interaction of Web proxy cache coherency and replacement policies using trace-driven simulations. We specifically examine the relative importance of each typ...
Balachander Krishnamurthy, Craig E. Wills
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
14 years 27 days ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
14 years 28 days ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek