328 search results - page 40 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
WAIM
2001
Springer
13 years 12 months ago
2001
Springer
Abstract. Broadcasting is a very effective technique to disseminate information to a massive number of clients when the data size is small. However, if the data size is large, the...
DATE
2010
IEEE
14 years 19 days ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- This paper presents an Application-Specific Instruction Set Processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra predic...