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» Improving Performance of Small On-Chip Instruction Caches
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CASCON
2008
164views Education» more  CASCON 2008»
13 years 9 months ago
High performance XML parsing using parallel bit stream technology
Parabix (parallel bit streams for XML) is an open-source XML parser that employs the SIMD (single-instruction multiple-data) capabilities of modern-day commodity processors to del...
Robert D. Cameron, Kenneth S. Herdy, Dan Lin
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
14 years 1 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
IPPS
2000
IEEE
13 years 12 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
CHES
2006
Springer
111views Cryptology» more  CHES 2006»
13 years 11 months ago
Cache-Collision Timing Attacks Against AES
This paper describes several novel timing attacks against the common table-driven software implementation of the AES cipher. We define a general attack strategy using a simplified ...
Joseph Bonneau, Ilya Mironov
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 4 months ago
Counter-Based Cache Replacement Algorithms
Recent studies have shown that in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin