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» Improving Performance of Small On-Chip Instruction Caches
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INFOCOM
2002
IEEE
14 years 18 days ago
Using the Small-World Model to Improve Freenet Performance
– Efficient data retrieval in a peer-to-peer system like Freenet is a challenging problem. In this paper we study the impact of cache replacement policy on the performance of Fre...
Hui Zhang 0002, Ashish Goel, Ramesh Govindan
HPCA
2009
IEEE
14 years 8 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...
DAC
2003
ACM
14 years 8 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
IEEEPACT
2009
IEEE
14 years 2 months ago
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
—Bulk memory copying and initialization is one of the most ubiquitous operations performed in current computer systems by both user applications and Operating Systems. While many...
Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar I...
SIGMOD
2004
ACM
204views Database» more  SIGMOD 2004»
14 years 7 months ago
Buffering Database Operations for Enhanced Instruction Cache Performance
As more and more query processing work can be done in main memory, memory access is becoming a significant cost component of database operations. Recent database research has show...
Jingren Zhou, Kenneth A. Ross