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ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
15 years 6 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
CONEXT
2008
ACM
15 years 6 months ago
A priority-layered approach to transport for high bandwidth-delay product networks
High-speed organizational networks running over leased fiber-optic lines or VPNs suffer from the well-known limitations of TCP over long-fat pipes. High-performance protocols like...
Vidhyashankar Venkataraman, Paul Francis, Murali S...
RECOMB
2010
Springer
15 years 6 months ago
naiveBayesCall: An Efficient Model-Based Base-Calling Algorithm for High-Throughput Sequencing
Immense amounts of raw instrument data (i.e., images of fluorescence) are currently being generated using ultra high-throughput sequencing platforms. An important computational cha...
Wei-Chun Kao, Yun S. Song
DAC
2008
ACM
15 years 6 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
DAC
2008
ACM
15 years 6 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
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