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ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
14 years 3 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas
ASAP
2004
IEEE
185views Hardware» more  ASAP 2004»
14 years 15 days ago
Families of FPGA-Based Algorithms for Approximate String Matching
Dynamic programming for approximate string matching is a large family of different algorithms, which vary significantly in purpose, complexity, and hardware utilization. Many impl...
Tom Van Court, Martin C. Herbordt
CORR
2011
Springer
206views Education» more  CORR 2011»
13 years 3 months ago
Arrangement Computation for Planar Algebraic Curves
We present a new certified and complete algorithm to compute arrangements of real planar algebraic curves. Our algorithm provides a geometric-topological analysis of the decompos...
Eric Berberich, Pavel Emeliyanenko, Alexander Kobe...
DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
14 years 3 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
ISCAS
1999
IEEE
206views Hardware» more  ISCAS 1999»
14 years 1 months ago
Transimpedance amplifier with differential photodiode current sensing
This paper presents a balanced receiver structure suitable for wireless infrared data communications. The receiver provides a fixed photodiode bias voltage with the use of a regul...
B. Zand, K. Phang, D. A. Johns