1045 search results - page 93 / 209 » Improving SHA-2 Hardware Implementations |
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
FPL
2009
Springer
14 years 2 months ago
2009
Springer
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
ASPDAC
1998
ACM
14 years 2 months ago
1998
ACM
This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
DATE
1997
IEEE
14 years 2 months ago
1997
IEEE
A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correc...