1045 search results - page 99 / 209 » Improving SHA-2 Hardware Implementations |
DATE
2004
IEEE
14 years 1 months ago
2004
IEEE
We show how to implement an arbitrary two-qubit unitary operation using any of several quantum gate libraries with small a priori upper bounds on gate counts. In analogy to librar...
TVLSI
2010
13 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
SIGOPS
2010
13 years 4 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
DAMON
2009
Springer
14 years 4 months ago
2009
Springer
Database engines face growing scalability challenges as core counts exponentially increase each processor generation, and the efficiency of synchronization primitives used to prot...