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» Improving Testing Efficiency using Cumulative Test Analysis
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VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 23 days ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
13 years 5 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...
PVLDB
2008
108views more  PVLDB 2008»
13 years 7 months ago
Taming verification hardness: an efficient algorithm for testing subgraph isomorphism
Graphs are widely used to model complicated data semantics in many applications. In this paper, we aim to develop efficient techniques to retrieve graphs, containing a given query...
Haichuan Shang, Ying Zhang, Xuemin Lin, Jeffrey Xu...
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
14 years 1 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
14 years 7 months ago
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, H...