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» Improving Testing Efficiency using Cumulative Test Analysis
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SIGDOC
2000
ACM
13 years 12 months ago
Testing documentation with "low-tech" simulation
∗ This paper introduces low-tech simulation as a technique for testing procedures and their documentation. The key idea is to test the interface-procedure-documentation set in th...
David G. Novick
BMCBI
2007
197views more  BMCBI 2007»
13 years 7 months ago
Boolean networks using the chi-square test for inferring large-scale gene regulatory networks
Background: Boolean network (BN) modeling is a commonly used method for constructing gene regulatory networks from time series microarray data. However, its major drawback is that...
Haseong Kim, Jae K. Lee, Taesung Park
ATS
1998
IEEE
91views Hardware» more  ATS 1998»
13 years 11 months ago
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
TC
1998
13 years 7 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
SIGCSE
2006
ACM
139views Education» more  SIGCSE 2006»
14 years 1 months ago
Closing the loop on test creation: a question assessment mechanism for instructors
New accreditation requirements focus on education as a “continuous improvement process.” The most important part of such a process is that information gets fed back into the s...
Titus Winters, Tom Payne