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DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
CCGRID
2001
IEEE
14 years 11 days ago
2001
IEEE
To ameliorate the need to spend significant programmer time modifying parallel programs to achieve highperformance, while maintaining compact, comprehensible source codes, this pa...
SAC
2006
ACM
14 years 2 months ago
2006
ACM
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper presents the optimization and evaluation of parallel I/O for the BIPS3D parallel irregular application, a 3-dimensional simulation of BJT and HBT bipolar devices. The p...
CGF
2006
13 years 8 months ago
2006
We present a novel algorithm to compute cache-efficient layouts of bounding volume hierarchies (BVHs) of polygonal models. Our approach does not make any assumptions about the cac...