1001 search results - page 32 / 201 » Improving memory hierarchy performance for irregular applica... |
148
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
216
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ISCA
2005
IEEE
15 years 11 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
168
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ASPLOS
2010
ACM
16 years 27 days ago
2010
ACM
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
183
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ISCA
2009
IEEE
16 years 21 days ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
134
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PATMOS
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. Embedded devices designed for various real-time multimedia and telecom applications, have a bottleneck in energy consumption and performance that becomes day by day more ...