1001 search results - page 46 / 201 » Improving memory hierarchy performance for irregular applica... |
199
Voted
CODES
2010
IEEE
15 years 3 months ago
2010
IEEE
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
157
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
168
Voted
WEA
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. Many large-scale optimization problems rely on graph theoretic solutions; yet high-performance computing has traditionally focused on regular applications with high degre...
151
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MICRO
2009
IEEE
16 years 23 days ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
181
Voted
OOPSLA
2009
Springer
16 years 20 days ago
2009
Springer
We present Chorus, a high-level parallel programming model suitable for irregular, heap-manipulating applications like mesh refinement and epidemic simulations, and JChorus, an i...