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ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
14 years 5 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
VR
2007
IEEE
150views Virtual Reality» more  VR 2007»
14 years 2 months ago
Tactile Feedback at the Finger Tips for Improved Direct Interaction in Immersive Environments
We present a new tactile feedback system for finger-based interactions in immersive virtual reality applications. The system consists of tracked thimbles for the fingers with shap...
Robert Scheibe, Mathias Moehring, Bernd Froehlich
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 1 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ICFP
2009
ACM
14 years 9 months ago
Partial memoization of concurrency and communication
Memoization is a well-known optimization technique used to eliminate redundant calls for pure functions. If a call to a function f with argument v yields result r, a subsequent ca...
Lukasz Ziarek, K. C. Sivaramakrishnan, Suresh Jaga...
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 5 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...