Sciweavers

271 search results - page 27 / 55
» Improving the Average Delay of Sorting
Sort
View
DAC
2008
ACM
14 years 8 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
ICCD
2006
IEEE
126views Hardware» more  ICCD 2006»
14 years 4 months ago
Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems
—In this paper we propose the method of task merging and idle period clustering for dynamic power management (DPM) in a real-time system with multiple processing elements. We sho...
Shaobo Liu, Qinru Qiu, Qing Wu
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 4 months ago
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus, multiple compatible bus transactions can be performed simultaneously with only a...
Ruibing Lu, Cheng-Kok Koh
NCA
2009
IEEE
14 years 2 months ago
Seed Scheduling for Peer-to-Peer Networks
—The initial phase in a content distribution (file sharing) scenario is delicate due to the lack of global knowledge and the dynamics of the overlay. An unwise distribution of t...
Flavio Esposito, Ibrahim Matta, Pietro Michiardi, ...
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low power FPGA routing architecture
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
Somsubhra Mondal, Seda Ogrenci Memik