271 search results - page 6 / 55 » Improving the Average Delay of Sorting |
AINA
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes an analytical model for delayed reservation scheme, which can be exactly analyzed. By applying it to a server-based QoS management network, we can obtain the r...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...