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TACO
2008
130views more  TACO 2008»
13 years 7 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
AIPS
2007
13 years 10 months ago
A Fast Incremental Algorithm for Maintaining Dispatchability of Partially Controllable Plans
Autonomous systems operating in real-world environments must be able to plan, schedule, and execute missions while robustly adapting to uncertainty and disturbances. Previous work...
Julie A. Shah, John Stedl, Brian C. Williams, Paul...
ICAS
2006
IEEE
143views Robotics» more  ICAS 2006»
14 years 2 months ago
Towards Autonomic Distribution of Existing Object Oriented Programs
By harnessing computational power of distributed heterogeneous resources, it is possible to build a large scale integrated system so that a centralized program is partitioned and ...
Debzani Deb, M. Muztaba Fuad, Michael J. Oudshoorn
DAC
2006
ACM
14 years 9 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
14 years 1 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...