Sciweavers

122 search results - page 17 / 25
» In Situ Design of Register Operations
Sort
View
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 6 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
EMSOFT
2005
Springer
14 years 3 months ago
HAIL: a language for easy and correct device access
It is difficult to write device drivers. One factor is that writing low-level code for accessing devices and manipulating their registers is tedious and error-prone. For many syst...
Jun Sun 0002, Wanghong Yuan, Mahesh Kallahalla, Na...
DAC
2006
ACM
14 years 10 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
CLEIEJ
2006
96views more  CLEIEJ 2006»
13 years 9 months ago
A Single-Version Algorithmic Approach to Fault Tolerant Computing Using Static Redundancy
This paper describes a single-version algorithmic approach to design in fault tolerant computing in various computing systems by using static redundancy in order to mask transient...
Goutam Kumar Saha
TCAD
2008
114views more  TCAD 2008»
13 years 9 months ago
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...