309 search results - page 16 / 62 » In-Network Cache Coherence |
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work...
IPPS
2000
IEEE
14 years 4 hour ago
2000
IEEE
This paper presents a new methodology for implementing fast synchronization on scalable cache-coherent multiprocessors, through the use of hybrid primitives. Hybrid primitives lev...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
IPPS
2000
IEEE
14 years 4 hour ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...