Sciweavers

42 search results - page 7 / 9
» Increasing Pipelined IP Core Utilization in Process Networks...
Sort
View
VMV
2001
131views Visualization» more  VMV 2001»
13 years 8 months ago
Shape Model and Threshold Extraction via Shape Gradients
Shape information is utilized by numerous applications in computer vision, scientific visualization and computer graphics. This paper presents a novel algorithm for exploring and ...
Roger C. Tam, Alain Fournier
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 1 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
HPDC
2012
IEEE
11 years 9 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
BMCBI
2010
139views more  BMCBI 2010»
13 years 6 months ago
A highly efficient multi-core algorithm for clustering extremely large datasets
Background: In recent years, the demand for computational power in computational biology has increased due to rapidly growing data sets from microarray and other high-throughput t...
Johann M. Kraus, Hans A. Kestler
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 4 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt