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ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
14 years 19 days ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
HPCA
2003
IEEE
14 years 7 months ago
Reconsidering Complex Branch Predictors
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
Daniel A. Jiménez
ISCA
1998
IEEE
108views Hardware» more  ISCA 1998»
13 years 11 months ago
Pipeline Gating: Speculation Control for Energy Reduction
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
Srilatha Manne, Artur Klauser, Dirk Grunwald
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 28 days ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin