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» Instruction Level Parallelism
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93
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ETS
2000
IEEE
121views Hardware» more  ETS 2000»
15 years 2 months ago
Increasing Access to Learning With Hybrid Audio-Data Collaboration
Internet enabled hybrid audio-data collaboration delivers high quality audio over telephone lines and data interaction over packet switched Internet connections, thus distributing...
Michael W. Freeman, Lawrence W. Grimes, J. Ray Hol...
HPCA
2009
IEEE
16 years 3 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...
92
Voted
ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
15 years 9 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
122
Voted
ASPLOS
1992
ACM
15 years 6 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 7 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft