2784 search results - page 31 / 557 » Instruction Level Parallelism |
ISCA
2000
IEEE
14 years 2 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
VIP
2000
13 years 11 months ago
2000
Series Parallel (SP) digraphs are a common method of representing instructions with partially ordered actions, but not always an ideal one, as relationships among groups of action...
CAMP
2005
IEEE
14 years 3 months ago
2005
IEEE
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
FDL
2003
IEEE
14 years 3 months ago
2003
IEEE
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...