18 search results - page 3 / 4 » Instruction Replication for Clustered Microarchitectures |
ISCA
2003
IEEE
14 years 20 days ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
IEEEPACT
2002
IEEE
14 years 9 days ago
2002
IEEE
This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...