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» Instruction Set Limitation in Support of Software Diversity
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CASES
2000
ACM
13 years 12 months ago
A first-step towards an architecture tuning methodology for low power
We describe an automated environment to assist a system-on-achip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, an...
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. L...
SIGUCCS
2003
ACM
14 years 26 days ago
Computing labs and technology classroom (CLTC) initiative: a model for distributed support
DePauw University is a small, liberal arts institution with 2200 undergraduate residential students and 222 faculty members, located in Greencastle, Indiana. The challenges of sup...
Lynda S. LaRoche, Julianne M. Miranda, Angela P. S...
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
13 years 11 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
ICS
2007
Tsinghua U.
14 years 1 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
14 years 1 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August