29 search results - page 4 / 6 » Integrating BIST Techniques for On-Line SoC Testing |
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
ETS
2011
IEEE
12 years 7 months ago
2011
IEEE
—In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...