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ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 26 days ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
15 years 8 months ago
Speeding up power estimation of embedded software
Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component of the embedded sys...
Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
ENTCS
2007
81views more  ENTCS 2007»
15 years 3 months ago
Error Diagnosis in Equivalence Checking of High Performance Microprocessors
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
Alper Sen
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
15 years 10 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
SLIP
2009
ACM
15 years 10 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim