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DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 3 months ago
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie...
DAC
2000
ACM
14 years 2 months ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
14 years 4 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
DAC
1999
ACM
14 years 2 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
14 years 3 months ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi