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SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
14 years 3 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
13 years 2 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
DAC
2000
ACM
14 years 11 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
CASES
2005
ACM
14 years 11 days ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
FCCM
2009
IEEE
316views VLSI» more  FCCM 2009»
14 years 2 months ago
An FPGA Implementation for Solving Least Square Problem
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...
Depeng Yang, Gregory D. Peterson, Husheng Li, Junq...