154 search results - page 7 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
DAC
1999
ACM
14 years 11 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ICCD
2002
IEEE
14 years 7 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
DAC
1997
ACM
14 years 2 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
DAC
1994
ACM
14 years 2 months ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
HEURISTICS
2002
13 years 10 months ago
2002
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...