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» Interconnect design for deep submicron ICs
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ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
14 years 3 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
HPCA
2009
IEEE
14 years 7 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
ISQED
2011
IEEE
398views Hardware» more  ISQED 2011»
12 years 10 months ago
Switching constraint-driven thermal and reliability analysis of Nanometer designs
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...
Srini Krishnamoorthy, Vishak Venkatraman, Yuri Apa...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 1 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
14 years 1 months ago
Developing Mesochronous Synchronizers to Enable 3D NoCs
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
Igor Loi, Federico Angiolini, Luca Benini