816 search results - page 19 / 164 » Interconnect design methods for memory design |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
ALC
1997
13 years 9 months ago
1997
In the context of the modular and incremental development of complex systems, viewed as interconnections of interacting components, new dimensions and new problems arise in the ca...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...