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ICCD
1994
IEEE
69views Hardware» more  ICCD 1994»
13 years 11 months ago
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules
This paper presents a simple and robust method of designing the lossy-transmission-line interconnects in a network for multichip modules. This method uses wire-sizing entirely to ...
Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
DAC
2009
ACM
14 years 2 months ago
Variational capacitance extraction of on-chip interconnects based on continuous surface model
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...
Wenjian Yu, Chao Hu, Wangyang Zhang
DAC
2001
ACM
14 years 8 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 1 months ago
Wire-driven microarchitectural design space exploration
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
ASPDAC
2004
ACM
119views Hardware» more  ASPDAC 2004»
14 years 1 months ago
A fast congestion estimator for routing with bounded detours
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang